SPI : Serial Peripheral Interface

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posted Sep 17, 2016, 6:56 AM by Rohit Bhaskar

The serial peripheral interface provided in the ATMEGA16/32 allows a high-speed synchronous data communication channel with other devices.The relevant pins on the ATMEGA are :

1. MOSI : Master Out,Slave In : Pin B,5 This line is used by the master to send out data to the slave.The Master always initiates any communication.

2. MISO : Master In,Slave Out : Pin B,6 This line is used by the slave to send data to the master.

3. SCK : Serial Clock : Pin B,7 This is the serial clock generator. Communication takes place only when the clock is working.The clock starts a cycle when the master initiates communication.

4. (~SS): Slave Select : Pin B,4 The slave will respond only if the Slave Select line is pulled low.If not pulled low,the chip will not read data even if keeps on receiving clock pulses.The Master pulls the Slave select line high again at the end of the data transfer to synchronise the slave.

Connections :

Master ------------------------------------------> Slave

MOSI ------------------------------------------> MOSI

SCK ------------------------------------------> SCK

~SS -------------------------------------------> ~SS

MISO <------------------------------------------ MISO

Data Flow :

The SPI supports a full duplex operation, which means communication can take place both ways simultaneously, i.e. data can be sent on one line and received on another line simultaneously.

When two-way communication is desired, it is best to follow the following method.

1. Write Data to the SPDR (SPI Data Register)
2. Wait till the transmission is complete. You can do this either by polling a flag or by using interrupts.
3. Read the SPSR (SPI Status Register) and then the SPDR immediately after that, in that order, if you are using the polling method. Just reading the SPDR is enough if you are using the interrupt example.This will prevent any accidental loss of data.

This can be done safely even with the slave, since the data which has been queued up in the SPDR will not be transmitted unless the Master initializes communication. However, iteration-based loops cannot be used in the case of the slave to send data, since it is unsure when the Master will initiate communication and so the data would keep on updating in the SPDR without being sent. It is thus advisable to use the interrupt method in case a transmission by the slave is desired.

Modes of Operation :

Click here to view the SPI Modes of operation

Control registers :

Bit 7 – SPIE : SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the global interrupt is enabled.

Bit 6 – SPE : SPI Enable
1 ----> SPI Enabled
0 ----> SPI Disabled

Bit 5 – DORD : Data Order
If DORD = 1 , the LSB of the data word is transmitted first.
If DORD = 0 , the MSB of the data word is transmitted first.

Bit 4 – MSTR : Master/Slave Select
MSTR = 0 ----> Slave Mode
MSTR = 1 ----> Master Mode

If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. MSTR will then have to be set again manually to re-enable SPI Master mode.

Bit 3 – CPOL : Clock Polarity
CPOL = 1 ----> SCK is high when idle
CPOL = 0 ----> SCK is low when idle

Bit 2 – CPHA : Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK.

Bits 1, 0 – SPR1, SPR0 : SPI Clock Rate Select 1 and 0

These control the SCK rate of the Master device and have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency (fosc) is shown in the following table:

Status Register :

Bit 7 – SPIF : SPI Interrupt Flag
This flag is set when a serial transfer is complete. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If ~SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding interrupt routine or it can be manually cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).

Bit 6 – WCOL : Write COLlision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register.

Bit 5..1 – Res : Reserved Bits

Bit 0 – SPI2X : Double SPI Speed Bit
When this bit is written to one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode . This means that the minimum SCK period will be two CPU clock periods, as opposed to the minimum of 4 in normal mode. When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4 or lower. The SPI interface on the ATmega16 is also used for program memory and EEPROM download- ing or uploading.